LT3476
BLOCK DIAGRAM
PV IN
33V
R SNS (EXT)
0.1
CAP
3, 4, 9, 10
EXTERNAL COMPONENTS
BUCK MODE
LED
2, 5, 8, 11
C BYP
2.2μF
LED ARRAY
C FILT
0.1μF
10μH
SW
22-29
+
35V
+
Q2
Q1 MAIN
V IN
3V
V ADJ
14, 15, 1.25V
36, 37
+
PWM
16, 17,
34, 35
IDLE MODE
VC
1, 12, 13, 38
V IN
33
REF
R SET
2k
A4
Q3
A1
ERROR
AMPLIFIER
THERMAL
LIMIT
145°C
R SET1
20k
ISRC
300μA
25k
RAMP
GENERATOR
OVERVOLTAGE
DETECT
PWM
A2
PWM
COMPARATOR
R
S
Q
DRIVER
+
A3
CURRENT SENSE
AMPLIFIER
SWITCH
R SW
0.02
7
1.05V
V1
Q4
200kHz
to 2MHz
OSCILLATOR
RT
6
NC
19, 20, 21
30, 31, 32
LT3476 CHANNEL
SHUTDOWN
SHDN
18
3476 BD
OPERATION
The LT3476 is a constant-frequency, current mode regula-
tor with an internal power switch. Operation can be best
understood by referring to the Block Diagram. At the
start of each oscillator cycle, the SR latch is set, which
turns on the Q1 power switch. A voltage proportional to
the switch current is added to a stabilizing ramp and the
resulting sum is fed into the positive terminal of the PWM
comparator, A2. When this voltage exceeds the level at
the negative input of A2, the SR latch is reset, turning off
the power switch. The level at the negative input of A2 is
set by the error amplifier A1, and is simply an amplified
version of the difference between the voltage across the
internal resistor R SET and the voltage across the external
current sense resistor R SNS . In this manner, the error
amplifier sets the correct peak switch current level to
regulate the current through R SNS . If the error amplifier’s
output increases, more current is delivered to the output;
if it decreases, less current is delivered.
6
The current regulated in R SNS can be adjusted by chang-
ing the voltage across R SET using the V ADJ input pin. The
amplifier A4 regulates current in Q3 to produce a voltage
across R SET equal to V ADJ . This current flowing through
transistor Q3 also produces a voltage across R SET one-
tenth the magnitude of the V ADJ input and level shifted to
the CAP input. The voltage across R SET is limited to 125mV
(typ) by the separate 1.25V input on A4.
The average current regulated in R SNS can also be adjusted
for dimming using the PWM pin. When the PWM pin is
low, switching is disabled and the error amplifier is turned
off so that it does not drive the VC pin. Also, all internal
loads on the VC pin are disabled so that the charge state
of the VC pin will be saved on the external compensation
capacitor. This feature reduces transient recovery time
because when the PWM input again transitions high, the
demand current for the switch returns to the value just
before PWM last transitioned low.
3476fb
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